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Hardware Acceleration of EDA Algorithms

Description

This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to extract automatically SIMD parallelism from regular uniprocessor code. With this approach, uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful, since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition.

Keywords

Hardware EDA Algorithms GPU CUDA Programming Model Boolean Satisfiability FPGA Static Timing Graphics Processors Fault Simulation Circuit GPU Code Kernel Generation Engine Constraints

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